Achieving timing closure of high-performance digital integrated circuits or systems implies obtaining sufficient timing performance from the circuit or system. This may mean, for example, being able to operate the clock fast enough to obtain the required performance, while guaranteeing functional correctness and limiting the total area occupied by or power consumed by the circuit or system. Methods for achieving timing closure typically include application of optimization techniques, including formal mathematical tuning of circuit parameters such as transistor widths or other heuristic optimization methods. Such methods either sequentially or simultaneously adjust a number of circuit parameters, such as transistor widths, in order to meet specific timing requirements or to minimize the clock period at which the circuit or system will operate, subject to a variety of constraints.
Changes made in one portion of a circuit or system will affect timing results in different portions of the circuit or system, and these effects must be considered in evaluating circuit changes. In one method of static timing analysis which is used to determine the minimum clock period at which a circuit or system can operate, the circuit or system is divided into circuit elements, which may be primitive logic gates, or collections of transistors which are to be treated as a single logical circuit element (i.e., channel-connected components, which are collections of transistors connected to each other through their sources and drains), and delays are computed between the inputs and outputs of each circuit element. Circuit element may also comprise larger subsystems for which abstracted or estimated delay models have been created. Hereafter the term gate will be understood to include collections of transistors which are to be treated as a single logical circuit element, and larger subsystems for which delay models have been created. Each such input to output connection for which a delay is computed is called a delay edge, and the graph of all signal nets and all delay edges between them is called the timing graph of the circuit or system. Often additional delay edges associated with signal nets are included in the timing graph to model wire or interconnect delay, and separate nodes are introduced at each gate input and output, but for simplicity these will be omitted here. It is understood that the methods described here are readily applied to these and other alternative timing graph formulations. Edge delays (delays of particular input-to-output transitions of a gate) are functions of many parameters, including the size of the transistors in the gate, the loading on the output of the gate, and the slew at the input of the gate. An edge slew, which is the time it takes for a signal propagated between the input and output connected by a delay edge to make a transition from 0 to 1 or from 1 to 0 (often measured as the time taken to go between 10% and 90% of the supply voltage), is also computed for each delay edge, with similar functional dependencies. The slew value at an input of a gate which is used to compute edge delays and edge slews from that input is derived from the edge slews of all edges feeding the gate input. In one common timing analysis method the slew value is the maximum of these edge slew values. The loading value at the output of a gate which is used to compute delays and edge slews to that output is a function of the sizes of the transistors in the gates fed by that output. The computed edge delays are used to determine arrival times (ATs), required arrival times (RATs), and slacks throughout the circuit or system. Timing values may be early mode, computed to determine whether any signals will arrive too early at any memory element or primary output (e.g., before the data from the previous cycle has been stored), or late mode, to determine the longest path through the circuit or system, and hence the minimum clock period at which the circuit or system will operate. In late mode analysis, the slack of an edge is the maximum amount by which the delay of the edge may be increased and still allow the circuit or system to operate at the specified clock period, and the slack of a node is the maximum amount by which the delay of any one edge feeding or fed by the node may be increased and still allow the circuit or system to operate at the specified clock period. Thus a negative slack indicates that the circuit or system will not operate at the specified clock period. The AT, RAT, and slack of a node in late mode analysis are:ATi=Maxj(ATj+dji)RATi=Mink(RATk−dik)Slacki=RATi−ATi
where dji are the delays of all edges whose sink is node i and dik are the delays of all edges whose source is node i.
Because the delays associated with rising and falling transitions of a net are typically different and have different dependencies on underlying gate parameters, separate ATs, RATs, and node slews are often computed for rising and falling transitions on a node in a circuit or system, and separate edge delays and edge slews are often computed for each possible combination of transitions on the source and sink of the edge. Separate ATs, RATs, and node slews may also be computed on a node to prevent improper combination of timing information associated with different clock phases, to facilitate false path analysis, or for other purposes well known to those skilled in the art, with separate edge delays and slews computed between such partitions of node data. It will therefore be understood hereafter that a timing node may refer to a particular combination of associated timing information on an electrical node of the circuit or system (e.g., the AT, RAT, and node slew associated with a rising signal launched by a particular clock phase), and an edge may refer to information propagated between a particular pair of nodes in the above sense (e.g., the edge delay and edge slew associated with the propagation of a rising transition at the edge source to a falling transition at the edge sink).
Thus a change to the sizes of transistors in a gate will affect the edge slews and edge delays through the gate, and because of the dependence of node slew on edge slew, edge slew on node slew, edge delay on node slew, and AT on edge delay and AT, it will also affect the slews, edge slews, edge delays, and ATs of all nodes and edges in the fanout cone of the gate. Because of the dependence of edge delay and edge slew on load, changes to the sizes of transistors in a gate will also affect the edge delays and edge slews of input gates feeding the gate, and these will in turn affect the node slews, edge slews, edge delays, and ATs of all nodes and edges in the fanout cone of the input gates. And because of the dependence of RAT on edge delay and RAT, changes to the sizes of transistors in a gate will also affect the RATs of all gates in the fanin cone of any gate in the union of the fanout cones of the input gates of the gate. The slack values of a node are affected anywhere that either the AT or RAT values are affected. All of these effects are seen in circuit 90 of FIG. 1, where a change is assumed to have been made to transistors 110 and 120 of gate 100, directly affecting the edge delays and edge slews of gate 100. These changes also affect the loading of input gate 130, and hence the edge delays and edge slews of gate 130, but because the sizes of transistors in gate 130 are unchanged, the edge delays and edge slews of gate 140 are unchanged. Because the output slew of gate 130 has changed, the edge delays and edge slews of gates of gates 150, 160, and 170 are also changed, as are the ATs at these gate outputs. All of these delay changes cause the RATs of the output nodes of gates 100, 130, 140, 160, 180, 190, 200, and 210 to be affected (the outputs of gates 150 and 170 are primary outputs (POs) and hence their RATs are fixed). However because gate 220 is not in the fanin cone of any gate in the fanout cone of gate 130, neither its edge slews, edge delays, AT, or RAT are affected. These influences are summarized in FIG. 2.
Many of the optimization techniques used to achieve timing closure have practical limits on the size of the circuit or system to which they can be applied, due to memory, runtime, or numerical noise, and are therefore typically applied to small partitions of a circuit or system. Such application requires partitioning of the circuit or system and establishment of constraints or assertions at the boundaries of these partitions, effectively blocking the flow of timing information, as described above, between the partitions and allowing them to be optimized separately. An example of this can be seen in FIG. 3, in which circuit 90 of FIG. 1 has been divided into partitions 300 and 310. ATs, slews, and load limits have been asserted inputs 320 and 330 of partition 310, while required arrival times (RATs), loads, and slew limits have been asserted at outputs 340 and 350 of partition 300. These assertions are set in such a way that if each partitions is modified so that the timing requirements imposed by the partition assertions are met, the timing requirements imposed by the overall circuit timing assertions will also be met. For example, the AT assertion for an input of a partition would typically be set to be greater than or equal to the RAT assertion at the output of the partition which feeds it. Similarly, since edge delay is generally an increasing function of both input slew and output load, a partition input slew assertion would be set to be greater than or equal to the corresponding partition output slew limit, and a partition input load limit would be set to be less than or equal to the corresponding partition output load. In general, in a late mode optimization which minimizes the delay of a circuit or attempts to meet an upper bound constraint on the circuit delay, the constraint limiting the allowed variation of a parameter on a first side of the partition boundary must not allow that parameter to change in a way that would result in a greater delay in an edge on the second side of the boundary than results from the parameter assertion on the second side of the boundary. While the above discussion referred to late mode timing analysis, similar boundary constraints and assertions can be used to allow partitioned early mode analysis and optimization. In early mode, the AT assertion for an input of a partition would typically be set to be less than or equal to the RAT assertion at the output of the partition which feeds it, and a constraint limiting the allowed variation of a parameter on a first side of the partition boundary must not allow that parameter to change in a way that would result in a smaller delay in an edge on the second side of the boundary than results from the parameter assertion on the second side of the boundary.
Such partitioning can cause disruption to other steps in the design process. In addition, any partition boundary constraints determined before optimization of the circuit or system partitions are unable to account for the effects of the subsequent optimization, and will therefore result in unequal effort being applied to different portions of critical paths cut by these partition boundaries, and thus in a sub-optimal result.
Thus there is a need for a method which allows optimization techniques to apply to portions of a circuit or system without partitioning.